Cascade Clock Dividers

Memory Circuits

327

Cascade Clock Divider

A clock signal is needed in order for sequential circuits to function. Usually the clock signal comes from a crystal oscillator on-board. The CPU used on Real Digital®’s Blackboard has a maximum frequency of 667 MHz and the FPGA clock frequency can go up to 200MHz. However, some peripheral controllers do not need such a high frequency to operate; thus, you will use D Flip-Flops to create clock dividers.

There is a simple circuit that uses D-FF to divide the clock frequency by half. The circuit is shown in Fig. 1 below.

Assume clkdiv is high initially. As din inverts the signal clkdiv, din is initially low. When the first rising edge of clock arrives, clkdiv is updated by the current din value and changes to ‘0’. As soon as clkdiv changes to ‘0’, din will be pulled up to logic ‘1’ by the inverter. When the next rising edge of clk occurs, clkdiv will change to logic ‘1’ and din will change back to ‘0’ after the propagation delay of the inverter. The waveform of the circuit in Fig. 2 above is shown on the right. As a result, the period of clkdiv (the time between two adjacent rising edges) doubles the period of clk (i.e., the frequency of clkdiv is half of the clk frequency).

With this circuit, we can actually divide the clock by cascading the previous circuit, as displayed in Fig. 2 below.

Each stage divides the frequency by 2. Suppose that the input clock frequency to the first stage is 100 MHz (1,000,000Hz). After the first stage, the frequency becomes $\dfrac{100MHz}{2} = 50MHz$. After the second stage, the frequency becomes $\dfrac{100MHz}{2 \cdot 2} = 25MHz$. After n stage, the frequency becomes:

$\dfrac{100MHz}{2^n} = \underbrace{\dfrac{100,000,000}{2 \cdot 2 \dotsc \cdot 2}}\_{n} Hz$

Important Ideas

• Usually the clock signal comes from a crystal oscillator on-board;
• Some peripheral controllers do not need a high frequency to operate;
• Each stage of Cascade Clock Dividers divides the frequency by 2.